module vga_ex(
			input clk,
			input rst,
			input key1,
			output vga_hs,
			output vga_vs,
			output R,
			output G,
			output B
		);

reg [6:0]cnt_t1;
reg [8:0]cnt_t2;
reg [7:0]cnt_t3;
reg flag_t2;
always @(posedge clk)
begin
	if(!rst)begin
		cnt_t1<=1;
	else if(cnt_t1==72) begin cnt_t1<=1; flag_t2<=1; end
   else if(!flag_t2)cnt_t1<=cnt_t1+1; 
end

always @(posedge clk)
begin
	if(!rst)
		cnt_t2<=1;
	else	if(cnt_t2<=312) begin cnt_t2<=1; flag_t2<=0;end
	else  if(flag_t2) cnt_t2<=cnt_t2+1;
end

always @(posedge clk)
begin
	if(!rst)
		cnt_t3<=1;
	else if(cnt_t1==72)
	if(cnt_t3<=144) begin cnt_t3<=1; flag_t4<=1;end
	else   cnt_t3<=cnt_t3+1;
end

always @(posedge clk)
begin
	if(!rst)
		cnt_t2<=1;
	else	if(cnt_t2<=312) begin cnt_t2<=1; flag_t2<=0;end
	else  if(flag_t2) cnt_t2<=cnt_t2+1;
end

